mirror of
https://github.com/juce-framework/JUCE.git
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455 lines
22 KiB
C++
455 lines
22 KiB
C++
/*
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==============================================================================
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This file is part of the JUCE library.
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Copyright (c) 2017 - ROLI Ltd.
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JUCE is an open source library subject to commercial or open-source
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licensing.
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By using JUCE, you agree to the terms of both the JUCE 5 End-User License
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Agreement and JUCE 5 Privacy Policy (both updated and effective as of the
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27th April 2017).
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End User License Agreement: www.juce.com/juce-5-licence
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Privacy Policy: www.juce.com/juce-5-privacy-policy
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Or: You may also use this code under the terms of the GPL v3 (see
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www.gnu.org/licenses).
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JUCE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY, AND ALL WARRANTIES, WHETHER
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EXPRESSED OR IMPLIED, INCLUDING MERCHANTABILITY AND FITNESS FOR PURPOSE, ARE
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DISCLAIMED.
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==============================================================================
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*/
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namespace juce
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{
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namespace dsp
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{
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#ifndef DOXYGEN
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// This class is needed internally.
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template <typename Scalar>
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struct CmplxSIMDOps;
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#endif
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//==============================================================================
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/**
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A wrapper around the platform's native SIMD register type.
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This class is only availabe on SIMD machines. Use JUCE_USE_SIMD to query
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if SIMD is avaialble for your system.
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SIMDRegister<Type> is a templated class representing the native
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vectorized version of FloatingType. SIMDRegister supports all numerical
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primitive types and std:complex<float> and std::complex<double> supports
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and most operations of the corresponding primitive
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type. Additionally, SIMDRegister can be accessed like an array to extract
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the individual elements.
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If you are using SIMDRegister as a pointer, then you must ensure that the
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memory is suffeciently aligned for SIMD vector operations. Failing to do so
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will result in crashes or very slow code. Use SIMDRegister::isSIMDAligned
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to query if a pointer is suffeciently aligned for SIMD vector operations.
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Note that using SIMDRegister without enabling optimizations will result
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in code with very poor performance.
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*/
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template <typename Type>
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struct SIMDRegister
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{
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//==============================================================================
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/** The type that represents the individual constituents of the SIMD Register */
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typedef Type ElementType;
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/** STL compatible value_type definition (same as ElementType). */
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typedef ElementType value_type;
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/** The corresponding primitive integer type, for example, this will be int32_t
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if type is a float. */
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typedef typename SIMDInternal::MaskTypeFor<ElementType>::type MaskType;
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//==============================================================================
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// Here are some types which are needed internally
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/** The native primitive type (used internally). */
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typedef typename SIMDInternal::PrimitiveType<ElementType>::type PrimitiveType;
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/** The native operations for this platform and type combination (used internally) */
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typedef SIMDNativeOps<PrimitiveType> NativeOps;
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/** The native type (used internally). */
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typedef typename NativeOps::vSIMDType vSIMDType;
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/** The corresponding integer SIMDRegister type (used internally). */
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typedef SIMDRegister<MaskType> vMaskType;
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/** The internal native type for the corresponding mask type (used internally). */
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typedef typename vMaskType::vSIMDType vMaskSIMDType;
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/** Wrapper for operations which need to be handled differently for complex
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and scalar types (used internally). */
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typedef CmplxSIMDOps<ElementType> CmplxOps;
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//==============================================================================
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/** The size in bytes of this register. */
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static constexpr size_t SIMDRegisterSize = sizeof (vSIMDType);
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/** The number of elements that this vector can hold. */
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static constexpr size_t SIMDNumElements = SIMDRegisterSize / sizeof (ElementType);
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vSIMDType value;
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//==============================================================================
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/** Returns the number of elements in this vector. */
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static constexpr size_t size() noexcept { return SIMDNumElements; }
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//==============================================================================
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/** Creates a new SIMDRegister from the corresponding scalar primitive.
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The scalar is extended to all elements of the vector. */
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inline static SIMDRegister JUCE_VECTOR_CALLTYPE expand (ElementType s) noexcept { return {CmplxOps::expand (s)}; }
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/** Creates a new SIMDRegister from the internal SIMD type (for example
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__mm128 for single-precision floating point on SSE architectures). */
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inline static SIMDRegister JUCE_VECTOR_CALLTYPE fromNative (vSIMDType a) noexcept { return {a}; }
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/** Creates a new SIMDRegister from the first SIMDNumElements of a scalar array. */
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inline static SIMDRegister JUCE_VECTOR_CALLTYPE fromRawArray (const ElementType* a) noexcept
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{
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jassert (isSIMDAligned (a));
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return {CmplxOps::load (a)};
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}
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/** Copies the elements of the SIMDRegister to a scalar array in memory. */
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inline void JUCE_VECTOR_CALLTYPE copyToRawArray (ElementType* a) const noexcept
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{
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jassert (isSIMDAligned (a));
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CmplxOps::store (value, a);
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}
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//==============================================================================
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/** Returns the idx-th element of the receiver. Note that this does not check if idx
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is larger than the native register size. */
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inline ElementType JUCE_VECTOR_CALLTYPE operator[] (size_t idx) const noexcept
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{
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jassert (idx < SIMDNumElements);
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return reinterpret_cast<const ElementType*> (&value) [idx];
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}
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/** Returns the idx-th element of the receiver. Note that this does not check if idx
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is larger than the native register size. */
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inline ElementType& JUCE_VECTOR_CALLTYPE operator[] (size_t idx) noexcept
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{
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jassert (idx < SIMDNumElements);
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return reinterpret_cast<ElementType*> (&value) [idx];
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}
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//==============================================================================
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/** Adds another SIMDRegister to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator+= (SIMDRegister v) noexcept { value = NativeOps::add (value, v.value); return *this; }
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/** Subtracts another SIMDRegister to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator-= (SIMDRegister v) noexcept { value = NativeOps::sub (value, v.value); return *this; }
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/** Subtracts another SIMDRegister to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator*= (SIMDRegister v) noexcept { value = CmplxOps::mul (value, v.value); return *this; }
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//==============================================================================
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/** Broadcasts the scalar to all elements of the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator= (ElementType s) noexcept { value = CmplxOps::expand (s); return *this; }
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/** Adds a scalar to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator+= (ElementType s) noexcept { value = NativeOps::add (value, CmplxOps::expand (s)); return *this; }
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/** Subtracts a scalar to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator-= (ElementType s) noexcept { value = NativeOps::sub (value, CmplxOps::expand (s)); return *this; }
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/** Multiplies a scalar to the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator*= (ElementType s) noexcept { value = CmplxOps::mul (value, CmplxOps::expand (s)); return *this; }
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//==============================================================================
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/** Bit-and the reciver with SIMDRegister v and store the result in the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator&= (vMaskType v) noexcept { value = NativeOps::bit_and (value, toVecType (v.value)); return *this; }
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/** Bit-or the reciver with SIMDRegister v and store the result in the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator|= (vMaskType v) noexcept { value = NativeOps::bit_or (value, toVecType (v.value)); return *this; }
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/** Bit-xor the reciver with SIMDRegister v and store the result in the receiver. */
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator^= (vMaskType v) noexcept { value = NativeOps::bit_xor (value, toVecType (v.value)); return *this; }
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//==============================================================================
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/** Bit-and each element of the reciver with the scalar s and store the result in the receiver.*/
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator&= (MaskType s) noexcept { value = NativeOps::bit_and (value, toVecType (s)); return *this; }
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/** Bit-or each element of the reciver with the scalar s and store the result in the receiver.*/
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator|= (MaskType s) noexcept { value = NativeOps::bit_or (value, toVecType (s)); return *this; }
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/** Bit-xor each element of the reciver with the scalar s and store the result in the receiver.*/
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inline SIMDRegister& JUCE_VECTOR_CALLTYPE operator^= (MaskType s) noexcept { value = NativeOps::bit_xor (value, toVecType (s)); return *this; }
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//==============================================================================
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/** Returns the sum of the receiver and v.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator+ (SIMDRegister v) const noexcept { return { NativeOps::add (value, v.value) }; }
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/** Returns the difference of the receiver and v.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator- (SIMDRegister v) const noexcept { return { NativeOps::sub (value, v.value) }; }
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/** Returns the product of the receiver and v.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator* (SIMDRegister v) const noexcept { return { CmplxOps::mul (value, v.value) }; }
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//==============================================================================
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/** Returns a vector where each element is the sum of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator+ (ElementType s) const noexcept { return { NativeOps::add (value, CmplxOps::expand (s)) }; }
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/** Returns a vector where each element is the difference of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator- (ElementType s) const noexcept { return { NativeOps::sub (value, CmplxOps::expand (s)) }; }
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/** Returns a vector where each element is the difference of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator* (ElementType s) const noexcept { return { CmplxOps::mul (value, CmplxOps::expand (s)) }; }
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//==============================================================================
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/** Returns the bit-and of the receiver and v. */
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator& (vMaskType v) const noexcept { return { NativeOps::bit_and (value, toVecType (v.value)) }; }
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/** Returns the bit-or of the receiver and v. */
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator| (vMaskType v) const noexcept { return { NativeOps::bit_or (value, toVecType (v.value)) }; }
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/** Returns the bit-xor of the receiver and v. */
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator^ (vMaskType v) const noexcept { return { NativeOps::bit_xor (value, toVecType (v.value)) }; }
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/** Returns a vector where each element is the bit-inverted value of the corresponding element in the receiver.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator~ () const noexcept { return { NativeOps::bit_not (value) }; }
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//==============================================================================
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/** Returns a vector where each element is the bit-and'd value of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator& (MaskType s) const noexcept { return { NativeOps::bit_and (value, toVecType (s)) }; }
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/** Returns a vector where each element is the bit-or'd value of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator| (MaskType s) const noexcept { return { NativeOps::bit_or (value, toVecType (s)) }; }
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/** Returns a vector where each element is the bit-xor'd value of the corresponding element in the receiver and the scalar s.*/
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inline SIMDRegister JUCE_VECTOR_CALLTYPE operator^ (MaskType s) const noexcept { return { NativeOps::bit_xor (value, toVecType (s)) }; }
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//==============================================================================
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is equal to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE equal (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::equal (a.value, b.value)); }
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is not equal to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE notEqual (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::notEqual (a.value, b.value)); }
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is less than to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE lessThan (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::greaterThan (b.value, a.value)); }
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is than or equal to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE lessThanOrEqual (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::greaterThanOrEqual (b.value, a.value)); }
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is greater than to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE greaterThan (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::greaterThan (a.value, b.value)); }
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/** Returns a SIMDRegister of the corresponding integral type where each element has each bit set
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if the corresponding element of a is greater than or equal to the corresponding element of b, or zero otherwise.
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The result can then be used in bit operations defined above to avoid branches in vector SIMD code. */
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static inline vMaskType JUCE_VECTOR_CALLTYPE greaterThanOrEqual (SIMDRegister a, SIMDRegister b) noexcept { return toMaskType (NativeOps::greaterThanOrEqual (a.value, b.value)); }
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//==============================================================================
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/** Returns a new vector where each element is the minimum of the corresponding element of a and b. */
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static inline SIMDRegister JUCE_VECTOR_CALLTYPE min (SIMDRegister a, SIMDRegister b) noexcept { return { NativeOps::min (a.value, b.value) }; }
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/** Returns a new vector where each element is the maximum of the corresponding element of a and b. */
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static inline SIMDRegister JUCE_VECTOR_CALLTYPE max (SIMDRegister a, SIMDRegister b) noexcept { return { NativeOps::max (a.value, b.value) }; }
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//==============================================================================
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/** Multiplies a and b and adds the result to c. */
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static inline SIMDRegister JUCE_VECTOR_CALLTYPE multiplyAdd (SIMDRegister a, const SIMDRegister b, SIMDRegister c) noexcept
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{
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return { CmplxOps::muladd (a.value, b.value, c.value) };
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}
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//==============================================================================
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/** Returns a scalar which is the sum of all elements of the receiver. */
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inline ElementType sum() const noexcept { return CmplxOps::sum (value); }
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//==============================================================================
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/** Checks if the given pointer is suffeciently aligned for using SIMD operations. */
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static inline bool isSIMDAligned (const ElementType* ptr) noexcept
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{
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uintptr_t bitmask = SIMDRegisterSize - 1;
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return (reinterpret_cast<uintptr_t> (ptr) & bitmask) == 0;
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}
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/** Returns the next position in memory where isSIMDAligned returns true.
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If the current position in memory is already aligned then this method
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will simply return the pointer.
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*/
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static inline ElementType* getNextSIMDAlignedPtr (ElementType* ptr) noexcept
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{
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return snapPointerToAlignment (ptr, SIMDRegisterSize);
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}
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#ifndef DOXYGEN
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static inline const ElementType* getNextSIMDAlignedPtr (const ElementType* ptr) noexcept
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{
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return snapPointerToAlignment (ptr, SIMDRegisterSize);
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}
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#endif
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private:
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static inline vMaskType JUCE_VECTOR_CALLTYPE toMaskType (vSIMDType a) noexcept
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{
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union
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{
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vSIMDType in;
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vMaskSIMDType out;
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} u;
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u.in = a;
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return vMaskType::fromNative (u.out);
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE toVecType (vMaskSIMDType a) noexcept
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{
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union
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{
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vMaskSIMDType in;
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vSIMDType out;
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} u;
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u.in = a;
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return u.out;
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE toVecType (MaskType a) noexcept
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{
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union
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{
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vMaskSIMDType in;
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vSIMDType out;
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} u;
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u.in = CmplxSIMDOps<MaskType>::expand (a);
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return u.out;
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}
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};
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//==============================================================================
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/* This class is used internally by SIMDRegister to abstract away differences
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in operations which are different for complex and pure floating point types. */
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// the pure floating-point version
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template <typename Scalar>
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struct CmplxSIMDOps
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{
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typedef typename SIMDNativeOps<Scalar>::vSIMDType vSIMDType;
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static inline vSIMDType JUCE_VECTOR_CALLTYPE load (const Scalar* a) noexcept
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{
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return SIMDNativeOps<Scalar>::load (a);
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}
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static inline void JUCE_VECTOR_CALLTYPE store (vSIMDType value, Scalar* dest) noexcept
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{
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SIMDNativeOps<Scalar>::store (value, dest);
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE expand (Scalar s) noexcept
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{
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return SIMDNativeOps<Scalar>::expand (s);
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}
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static inline Scalar JUCE_VECTOR_CALLTYPE sum (vSIMDType a) noexcept
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{
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return SIMDNativeOps<Scalar>::sum (a);
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE mul (vSIMDType a, vSIMDType b) noexcept
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{
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return SIMDNativeOps<Scalar>::mul (a, b);
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE muladd (vSIMDType a, vSIMDType b, vSIMDType c) noexcept
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{
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return SIMDNativeOps<Scalar>::multiplyAdd (a, b, c);
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}
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};
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// The pure complex version
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template <typename Scalar>
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struct CmplxSIMDOps<std::complex<Scalar>>
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{
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typedef typename SIMDNativeOps<Scalar>::vSIMDType vSIMDType;
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static inline vSIMDType JUCE_VECTOR_CALLTYPE load (const std::complex<Scalar>* a) noexcept
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{
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return SIMDNativeOps<Scalar>::load (reinterpret_cast<const Scalar*> (a));
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}
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static inline void JUCE_VECTOR_CALLTYPE store (vSIMDType value, std::complex<Scalar>* dest) noexcept
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{
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SIMDNativeOps<Scalar>::store (value, reinterpret_cast<Scalar*> (dest));
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}
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static inline vSIMDType JUCE_VECTOR_CALLTYPE expand (std::complex<Scalar> s) noexcept
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{
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const int n = sizeof (vSIMDType) / sizeof (Scalar);
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union
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{
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vSIMDType v;
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Scalar floats[n];
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} u;
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for (int i = 0; i < n; ++i)
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u.floats[i] = (i & 1) == 0 ? s.real() : s.imag();
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return u.v;
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}
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static inline std::complex<Scalar> JUCE_VECTOR_CALLTYPE sum (vSIMDType a) noexcept
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{
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vSIMDType result = SIMDNativeOps<Scalar>::oddevensum (a);
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auto* ptr = reinterpret_cast<const Scalar*> (&result);
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return std::complex<Scalar> (ptr[0], ptr[1]);
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}
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|
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static inline vSIMDType JUCE_VECTOR_CALLTYPE mul (vSIMDType a, vSIMDType b) noexcept
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{
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return SIMDNativeOps<Scalar>::cmplxmul (a, b);
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}
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|
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static inline vSIMDType JUCE_VECTOR_CALLTYPE muladd (vSIMDType a, vSIMDType b, vSIMDType c) noexcept
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|
{
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|
return SIMDNativeOps<Scalar>::add (a, SIMDNativeOps<Scalar>::cmplxmul (b, c));
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}
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|
};
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|
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//==============================================================================
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|
#ifndef DOXYGEN
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|
namespace util
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|
{
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|
template <typename Type>
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inline void snapToZero (SIMDRegister<Type>&) noexcept {}
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|
}
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|
#endif
|
|
|
|
} // namespace dsp
|
|
|
|
// Extend some common used global functions to SIMDRegister types
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|
template <typename Type>
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|
inline dsp::SIMDRegister<Type> JUCE_VECTOR_CALLTYPE jmin (dsp::SIMDRegister<Type> a, dsp::SIMDRegister<Type> b) { return dsp::SIMDRegister<Type>::min (a, b); }
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|
template <typename Type>
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|
inline dsp::SIMDRegister<Type> JUCE_VECTOR_CALLTYPE jmax (dsp::SIMDRegister<Type> a, dsp::SIMDRegister<Type> b) { return dsp::SIMDRegister<Type>::max (a, b); }
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|
|
|
} // namespace juce
|